1. Field of the Invention
The present invention relates to the field of integrated circuit design, specifically to the integration of peripheral components and macro functions with a central processing unit (CPU) or user-customizable microprocessor.
2. Description of Related Technology
Modern control theory has had a major impact on a number of industrial disciplines and applications. The need to provide cost-effective implementation of control systems becomes evident especially in high-performance electromechanical applications. Some examples can be found in industrial drives, automotive and aerospace control, where controllers are usually embedded into the system. Embedded real-time control applications, such as those targeted at linear time invariant (LTI) control, are particularly demanding since the calculations must often be performed to meet hard time deadlines.
The selection of a specific technology for a controller application is affected in part by the required speed and arithmetic factors derived for the control algorithm, resulting in a variety of different combinations of algorithms, hardware, and software. The availability of control processing solutions, which are both efficient and straightforward to use, are important elements for the achievement of robust and cost-effective solutions. Separate high-MIPS digital signal processors (DSPs) are commonly used to perform the demanding real-time calculations referenced above.
Unfortunately, when the controller is implemented using traditional such prior art architectures, the control algorithm often has to be artificially partitioned and constrained, via programming, to meet the physical bus widths and mapping on the instruction set.
Numerous instances of prior art controllers utilizing DSP or ASIC technology in the implementation of state-space control algorithms exist. For example, U.S. Pat. No. 6,490,118 to Ell, et al. issued Dec. 3, 2002, and entitled “Adaptive h-infinity hardware controller for disc drive actuator control” discloses apparatus and methods for generating control inputs for a disc drive dual stage actuator. An h-infinity hardware controller generates the control inputs in relation to an actual position signal, a desired position signal and a unique set of coefficients. The coefficients are selected by obtaining an output response, selecting the coefficients in relation to the output response, and storing the coefficients in a nonvolatile memory location. An ASIC implementing a state-space controller functionality is also disclosed.
A number of other controller architectures and development technologies have been suggested as well. For example, U.S. Pat. No. 6,101,058 to Morris issued Aug. 8, 2000 and entitled “Method of implementing a linear discrete-time state-space servo control system on a fixed-point digital signal processor in a disc drive” discloses a method of implementing a model based servo controller in a digital signal processor in a disc drive. The method comprises obtaining matrices for a discrete-time state-space realization of the servo controller. Controller states of the controller are scaled to reduce a worst case bound on the controller states. The controller states are transformed to a desired format which reduces a number of required mathematical operations. Further, the matrices are converted to fixed point format.
U.S. Pat. No. 5,920,478 to Ekblad, et al. issued Jul. 6, 1999 entitled “Multi-input multi-output generic non-interacting controller” discloses a multi-input multi-output (MIMO) controller which is configured as a generic, non-interacting, multivariable controller with adaptive capabilities. The controller transforms the coupled multivariable control problem to multiple decoupled single-input single-output loops. The decoupling occurs in the input/output map of the system being controlled. The transformed system can then be controlled using any control synthesis technique to meet the system performance objectives, such as Proportional plus Integral plus Derivative (PID) control. An empirical dynamic model is continually identified from on-line data. From this model, static decoupling transformations based on a singular value decomposition are determined and updated and the controller gains are calculated.
U.S. Pat. No. 5,978,752 to Morris issued Nov. 2, 1999 entitled “Model validation algorithm for characterizing parameters and uncertainty in a disc drive” discloses a system and method for validating a model used in implementing a model-based servo controller in a disc drive. A nominal model is first constructed. The nominal model is augmented with an uncertainty description to characterize variations in drives to be manufactured. The model is constrained by performance objectives. Weights corresponding to the uncertainty description and performance objectives are adjusted based on a comparison between first and second matrix functions until a desired performance level is achieved while maintaining stability in a desired frequency range.
U.S. Pat. No. 5,796,920 to Hyland issued Aug. 18, 1998 entitled “Multiprocessor system and method for identification and adaptive control of dynamic systems” discloses a system and method for identifying and adapting a control system for a dynamic system. In one embodiment, massively parallel, decentralized signal processing equipment is disclosed which can (1) identify a dynamic system; (2) adapt an on-line control system for the dynamic system; and/or, (3) solve off-line complex, nonlinear problems related to either static or dynamic systems. The disclosed system optionally includes a neural network in which the neurons are two-way devices (forward and backward signal paths), each of which has a synaptic weight which is independently adjusted using only the forward and backward signals.
U.S. Pat. No. 5,796,919 to Kubica issued Aug. 18, 1998 and entitled “Method of constructing and designing fuzzy controllers” discloses a method of constructing and designing a fuzzy controller based on converting a finite dimensional linear controller to a fuzzy controller. After the fuzzy controller is created, it can be enhanced using heuristic knowledge. The fuzzy controller is constructed or designed using a microprocessor to calculate a defuzzified output based on singleton fuzzification, product inferencing and centroidal defuzzification.
U.S. Pat. No. 6,404,581 to Shah issued Jun. 11, 2002 entitled “Adaptation to unmeasured variables” discloses a scheme for management of uncertainty in control systems that require adaptation. The scheme seeks to remove as much uncertainty as possible at design time and manufacturing time by taking advantage of available compute resources in pre-computing a large set of robustness-performance tradeoff based model controllers at different operating conditions for different values of uncertainty parameters that occur in-use and in manufacturing. A group of control models, and corresponding model controllers with an uncertainty bound larger than the best-tuned controller, are generated. A subset of the model controllers is implemented in the system at manufacturing time based on characterization of the system. The subset of model controllers is switched at run time based on transient information received during operation of the system. See also United States Patent Application No. 20010014834 published Aug. 16, 2001.
U.S. Pat. No. 6,207,936 to de Waard, et al. issued Mar. 27, 2001 entitled “Model-based predictive control of thermal processing” discloses a nonlinear model-based predictive temperature control system. A multivariable temperature response is predicted using a nonlinear parameterized model of a thermal process reactor. The nonlinear parameterized model is implemented using a neural network. Predictions are made in an auto-regressive moving average fashion with a receding prediction horizon. Model predictions are incorporated into a control law for estimating the optimum future control strategy. The high-speed, predictive nature of the controller renders it advantageous in multivariable rapid thermal processing reactors where fast response and high temperature uniformity are needed.
“Designing and programming the emotion engine”, Masaaki Oka, Masakazu Suzuoki, Sony Computer Entertainment, IEEE Journal, November-December 1999, discloses a home gaming system controller architecture consisting of a graphics synthesizer, “Emotion Engine,” an I/O processor (IOP), and a sound-processing unit (SPU). The IOP controls peripheral devices such as a controller and a disk drive and detects controller input, which is sent to the Emotion Engine. The Emotion Engine consists of three independent processors. One is a traditional MIPS-based processor with a floating-point coprocessor, which is the overall controller. The others are floating-point vector processors. The data memory and the floating-point registers have a 128-bit width interface with the 128-bit registers divided into four 32-bit fields (x, y, z, w). Four floating-point multiply-adder-calculators (FMACs) are applied to each field respectively. The throughput of an FMAC is one clock cycle. This means the VPU can execute the following vector calculation in one cycle:x3=x0·x1+x2y3=y0·y1+y2z3=z0·z1+z2w3=w0·w1+w2The instruction memory is 64 bits wide; one instruction consists of 32-bit upper and lower fields that execute on the same clock cycle. The upper field controls the FMACs, and the lower controls the loadstore functions as well as the divider.
As evidenced by the foregoing broad spectrum of representative approaches, prior art controller schemes are not generally optimized in a fashion which allows adaptive modification of the underlying controller platform hardware and instruction set to suit controller algorithm function or properties. Specifically, the prior art in effect approaches the problem backwards, specifying a platform (such as a floating or fixed point DSP), and then seeking to adapt the control function to the specific architecture or hardware attributes of the selected platform. The intrinsic power of the extensible or “user-configurable” RISC processor to provide the necessary adaptation to the selected controller model has to date not been harnessed.
Furthermore, these prior art solutions are typically not optimized for control applications which generally tend to have a very limited number of specific functions (e.g., state-space models), thereby necessitating additional hardware and instructions, as well as attendant increased power consumption, gate count, and die size.
Based on the foregoing, what is needed is an improved method and apparatus for implementing control algorithms (such as LTI algorithms) which meets the simultaneous goal of a significantly reduced instruction set and cycle count associated with controller operations, while also optimizing other design criteria such as gate count and power consumption. Such improved method and apparatus would allow the controller designer to select the control functionality or algorithm best adapted for the application(s) at hand, and then easily tailor a cycle-, silicon-, and power-efficient processor solution which is optimized for that particular control algorithm. These capabilities would enable the designer to readily model real-time control algorithms, as well as other types of applications, without the need for a separate DSP or floating point unit.